1. Technical Field of the Invention
The present invention relates to a semiconductor device that is capable of performing a normal operation mode and a test mode, and to an electronic apparatus using the semiconductor device. More particularly, the present invention relates to a semiconductor device such as a gate array that does not require a test pin.
2. Description of Related Art
Conventionally, an integrated circuit (IC) having a function to test its internal circuit is provided with test pins that are exclusively used to control switching between a test mode and a normal operation mode. The test mode is conducted by the IC manufacturer to determine the acceptability of integrated circuits before they are shipped out. Therefore, the test pints are not required by the user who purchases the ICs.
The number of pins on an IC is restricted by the circuit size and the specification of the IC. In some cases, no space may be available to provide test pins exclusively used for the test. If this happens, and an IC has a plurality of power source pins, the number of the power source pins is reduced, and test pins are provided in place of the reduced power source pins. However, when the number of test pins cannot be reduced because of, for example, the user""s specification, the IC manufacture has to give up implementing the test mode.
Japanese Laid-open patent application HEI 2-62783 describes a semiconductor memory device having an aging mode and a plural-bit parallel test mode. The reference describes that the aging mode and the test mode can be simultaneously conducted only when a voltage higher than a predetermined voltage, e.g., a power supply voltage is applied to pins that become unnecessary in the aging mode and the test mode.
FIG. 7 shows a circuit diagram of a conventional semiconductor device of the type described in the reference. In the semiconductor device in FIG. 7, an input signal that is applied to an input terminal 10 is supplied to internal cells through inversion buffer circuits 12 and 14. In the normal operation mode, an input signal has voltage levels ranging from 0 V to a power supply voltage VDD. On the other hand, when the test mode is started, an input signal inputted in the input terminal 10 has a high voltage HVDD. The high voltage HVDD is provided through K number (K=3 in FIG. 7) of N-type transistors 20, 22 and 24 to an inversion buffer circuit 30 that is formed from a P-type transistor 32 and an N-type transistor 34. Further, an output from the inversion buffer circuit 30 is inputted in an inversion buffer circuit 40 that is formed from a P-type transistor 42 and an N-type transistor 44. An output from the inversion buffer circuit 40 is a test control signal.
When a threshold voltage of each of the N-type transistors 20, 22 and 24 is VTHN, and an inverse logic level of the inversion buffer circuit 30 is VINV, the following conditions need to be met:
VDDxe2x88x92Kxc2x7VTHN less than VINVxe2x80x83xe2x80x83(1)
HVDDxe2x88x92Kxc2x7VTHN greater than VINVxe2x80x83xe2x80x83(2)
When the formula (1) is satisfied, an input signal having a voltage lower than the power supply voltage VDD functions only as an input signal to the internal cells (in the normal operation mode). When the formula (2) is satisfied, an input signal having a high voltage HVDD functions as a test control signal, such that the semiconductor device goes in the test mode.
However, in the semiconductor device shown in FIG. 7, when an input signal having a voltage equal to the power supply voltage VDD is applied to the input terminal in the normal operation mode, a drain current (through-current) of several mA flows through the inversion buffer circuit 30. When this type of through-current flows in the normal operation mode, the power consumption is increased.
Semiconductor devices similar to the semiconductor device shown in FIG. 7 are described in Japanese Laid-open patent applications SHO 61-292755, HEI 1-245499 and HEI 2-3145. They suffer similar problems in that the power consumption likewise increases in the normal operation mode.
In view of the above, it is an object of the present invention to provide a semiconductor device in which its normal input pins are provided with a function of test pins, but the power consumption does not increase in the normal operation mode.
A semiconductor device in accordance with one embodiment of the present invention has a peripheral cell region and an internal cell region. The peripheral cell region comprises; a signal input terminal that inputs input signals having different voltage levels in a normal operation mode and when a test mode is started; a first transmission circuit that outputs the input signal in the internal cell region; a second transmission circuit that outputs a control signal indicating a test mode when the input signal has a voltage level equivalent to a voltage to be provided at starting the test mode; and a control circuit that cuts off current that flows in the second transmission circuit when the input signal has a voltage level to be provided in the normal operation mode.
In one embodiment of the present invention, a signal input terminal is commonly used in the normal operation mode and the test mode, and an input to the signal input terminal is transmitted through the first transmission circuit to the internal cell region. When an input signal having a voltage level that is different from a voltage level in the normal operation mode is inputted when the test mode is started, a control signal indicating the test mode is outputted from the second transmission circuit. However, when an input signal has a voltage level that is equal to a voltage level provided in the normal operation mode, the current that flows in the second transmission circuit is cut off by the control circuit. As a result, the power consumption is not increased.
The second transmission circuit outputs a control signal indicating the test mode when the input signal has a voltage level higher than a predetermined voltage level. The control circuit cuts off current flowing through the second transmission circuit when the input signal has a voltage level lower than the predetermined voltage level.
In this case, the control circuit may preferably include a first P-type transistor formed in a floating N-type well. A power supply voltage is provided to a gate of the first P-type transistor, a source of the first P-type transistor connects to the signal input terminal, and a drain of the first P-type transistor connects to an input terminal of the second transmission circuit.
In the normal operation mode, the first P-type transistor is turned off, and thus the current flowing through the second transmission circuit is cut off. The first P-type transistor is turned on when the test mode is started. However, since the P-type transistor is formed in the floating N-type well, no leakage current flows.
The control circuit may preferably include a second P-type transistor formed in the floating N-type well. The input signal is supplied to a gate of the second P-type transistor, the power supply voltage is supplied to a source of the second P-type transistor, and a drain of the second P-type transistor connects to the N-type well. The second P-type transistor is turned on during the normal operation mode, such that the potential of the floating N-type well is clamped generally at the power supply voltage.
When this type of P-type transistor is used, the predetermined voltage level may be set at a voltage level higher than the power supply voltage. As a result, the first P-type transistor can be turned on when the test mode is started.
The second transmission circuit may be structured to output a control signal indicating the test mode when the input signal has a voltage level lower than a predetermined voltage level. The control circuit may be structured to cut off current flowing through the second transmission circuit when the input signal has a voltage level that exceeds the predetermined voltage level. In this case, the control circuit may preferably have first and second N-type transistors formed in a floating P-type well. In this case, when the predetermined voltage level is lower than the level of the power supply voltage, the first N-type transistor can be turned on when the test mode is started.
Each of the first and second transmission circuits may be composed of a buffer circuit. As a result, an accurate logic can be transmitted in a short time even when the transmission path is long.
An electronic apparatus in accordance with another embodiment can implement therein a semiconductor device described above. The electronic apparatus can reduce its power consumption. Therefore, the electronic apparatus of the present invention may preferably be implemented in hand-carry type electronic apparatuses.